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Senior Design Verification Engineer – EVA Power Aware
Recruitment Consultant
Liam Geary
Contact Details
Posted
4 months ago
Senior Design Verification Engineer – Power Aware
Key Responsibilities
- Architect and implement SystemVerilog/UVM testbenches for complex video and computer vision IP blocks.
- Develop and validate power-aware testbenches using UPF, ensuring low-power design intent is accurately captured and verified.
- Write and maintain UVM sequences for functional and power-aware scenarios.
- Execute power-aware simulations, gate-level simulations, and formal verification.
- Collaborate cross-functionally with RTL, DFT, PD, and firmware teams to ensure full verification coverage.
- Debug and resolve issues across simulation and post-silicon environments.
- Automate regression environments using Python, Perl, or similar scripting languages.
- Drive KPIs related to system performance, area, and power metrics.
- Lead technical challenges and mentor junior engineers.
Minimum Qualifications
- Bachelor’s/Master’s degree in Computer/Electrical Engineering, Computer Science, or related field with 5 + years of relevant experience
Preferred Qualifications
- Strong expertise in Unified Power Format (UPF) and power-aware verification methodologies.
- Proven track record of successful tapeouts and post-silicon debug.
- Proficiency in C++/Python for firmware interaction and test content generation.
- Background in computer vision, multimedia, or video processing hardware.
- Experience working in large matrixed organizations and interacting with senior leadership.
- Demonstrated technical leadership in cross-functional teams.
Industry
Semiconductor
Contract Type
Permanent
Location
Ireland
City
Cork
Work Model
On-Site
Apply Now
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