Staff Senosrs Design Verification Engineer

About The Role

Qualcomm offers flexible work options tailored to our employee’s needs. These include a combination of work from home and working in our brand new, state of the art office in Penrose Dock, Cork.

Well-being and life balance are fundamental to Qualcomm as an employer.  We recognise and understand that employees have missed spending quality time with loved ones and extended family. 

As such, Cork Qualcomm policy allows our employees to blend short-term remote working with annual leave.

As a leading technology innovator, Qualcomm pushes the boundaries of what’s possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

The position is technology focused and involves participation in a broad range of sensors systems engineering activities within the Sensors Technologies group

Responsibilities will include:

• Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification
• Developing Testbenches and Verification Components such as UVCs, C models,  and Vertical/Horizontal re-usable Verification Environments.
• Verifying sensor algorithms RTL for ASIC tapeout quality delivery
• Test plan development based on Design documents and interaction with design/systems engineers
• Implementing C model integration within UVM framework.
• Writing SystemVerilog assertions
• Debugging, verifying, optimizing, and bit-exact matching with test vectors
• Analyzing coverage data and working with Design teams to address coverage holes
• Develop/augment framework for running regressions
• Debugging regression failures with design/Systems teams
• Support integration of design in higher-level subsystem including test planning, test vector delivery, and debug of test vectors at the integration level
• Python automation for improving workflows and team efficiency
• Participate in all project reviews
• Supporting software and other teams with debug
• Documentation

What are we looking for?

• Bachelor’s degree in Science, Engineering, or related field.
• 6+ years ASIC design verification, UVM-based functional verification, or related work experience.
• Experience using formal verification tools like Jasper or VC_Formal is a plus
• Experience with SystemC and Matlab are a plus.
• Gate level Simulation debug and usage of power extraction tools is a plus
• Experienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodology
• Experienced with Assertions like System Verilog Assertions
• Experience with debugging test failures and report verification result to achieve the expected code/functional/line coverage goals
• Extensive usage of RTL simulation tools.
• UVM,  System Verilog, Perl/Python shell-scripting skills required
• Familiarity with C/C++
• Strong analytical skills and ability to work in a dynamic and fast paced team environment
• Excellent written and verbal skills
• Strong interpersonal skills and a good team player