GPU Chief Architect or XPU Lab Director

GPU Chief Architect / Lab Director

Position Overview

A leading semiconductor research organization is seeking a GPU Chief Architect / Laboratory Director to define and lead the next generation of mobile and heterogeneous compute architectures.

This role focuses on the convergence of graphics processing units and AI accelerators into a unified compute subsystem designed to support emerging graphics and AI workloads. The position requires deep expertise in GPU microarchitecture, strong system-level architectural thinking across hardware and software, and proven experience delivering complex silicon products.

The successful candidate will shape the architecture of future mobile compute platforms, optimizing performance, energy efficiency, and silicon area while enabling new capabilities for AI-native workloads.

Key Responsibilities

Converged Compute Architecture Design

• Analyze emerging graphics and AI workloads using first-principles architectural thinking.

• Define a unified or partially unified heterogeneous compute architecture combining graphics and AI acceleration capabilities.

• Ensure compatibility or smooth transition from existing architectures to next-generation designs.

• Design unified or shared execution resources such as vector, scalar, and tensor processing units.

• Develop shared scheduling and workload dispatch mechanisms for mixed graphics and AI workloads.

• Design strategies for resource sharing and isolation under heterogeneous workloads.

• Evaluate architectural trade-offs between dedicated accelerators and unified compute blocks.

Mobile GPU Architecture Leadership

• Define and drive the roadmap for next-generation mobile GPU architecture.

• Lead architectural evolution of shader cores, execution pipelines, and memory subsystems.

• Optimize performance, power efficiency (performance per watt), and silicon area efficiency.

• Provide architectural leadership from early concept through silicon implementation and validation.

Memory and Interconnect Architecture

• Define memory hierarchy strategies optimized for heterogeneous compute workloads.

• Design shared cache architectures and bandwidth arbitration mechanisms.

• Optimize on-chip interconnect networks for mixed compute traffic patterns.

• Minimize data movement overhead between compute domains.

System-Level Architecture Collaboration

• Collaborate with CPU architects, AI software teams, runtime developers, and system architects.

• Participate in SoC-level design trade-offs including power, thermal management, and floorplanning.

• Align hardware architecture with modern graphics APIs and AI frameworks.

• Support performance modelling, workload characterization, and silicon bring-up activities.

Required Qualifications

• At least 15 years of experience in GPU architecture, AI accelerators, or heterogeneous computing systems.

• Deep expertise in GPU microarchitecture, including:

  • SIMD/SIMT execution models

  • Scheduling mechanisms

  • Memory hierarchies

• Strong knowledge of tensor and matrix computation used in AI acceleration.

• Proven experience delivering high-volume semiconductor products.

• Extensive experience with performance modelling and power optimization techniques.

• Strong leadership skills with the ability to coordinate cross-functional engineering teams.

• Excellent communication skills and ability to influence architectural direction across organizations.

Preferred Experience

• Experience designing converged heterogeneous compute systems.

• Background in mobile or power-constrained architectures.

• Knowledge of AI frameworks, graphics APIs, and runtime systems.

• Experience leading architectural teams or research laboratories.