Senior ASIC Verification Engineer

Senior ASIC Verification Engineer
Sunnyvale, CA

Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different environments with the ability to quickly learn and then solve complex problems. We are a system solution company that specializes in the design of industry-leading high-performance, low-power AI inferencing. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for many markets. We are at the leading edge of advancing the latest research and product improvements for Al inference solutions that will make Al even more advantageous for compelling new applications.

About the role:

• As a senior member of the ASIC team, you will be responsible for the pre-silicon correctness and quality of a high-performance and low-power convolutional neural network accelerator ASIC that forms the core of the company’s flagship perception module product for autonomous driving applications.
• This ASIC’s design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to form an end-to-end vision perception module that achieves record- breaking computational performance at low power.
• Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular System Verilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow.

Responsibilities:

• Ensure the pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and 3rd-party SoC IP blocks.
• SoC/Subsystem verification of embedded CPUs such as ARM/RISC-V and interconnect subsystem (including C and assembly diag validation)
• Develop the block-level, sub-system and full-chip verification environment and tests to implement test plans.
• Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the design-under-test work under all specified circumstances.
• Triage and debug functional and performance issues with the design-under-test.
• Handle bug tracking and coverage convergence.
• Perform diagnostic and post-silicon validation tests in the lab.

Required Qualifications:

• Knowledge of ARM/MIPS/RISC-V Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
• Familiarity with AMBA/APB/AXI Protocol
• Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C ….
• Excellent Verilog/System Verilog programming skills.
• Experience with UVM (or similar).
• Deep understanding of object oriented programming principles, constrained random stimulus, and a coverage driven verification approach.
• Scripting experience (Python, Perl, TCL, shell programming) highly-desirable.
• Interest to explore AI architectures for convolution, transformer and other kinds of workloads
• Self-starter and highly-motivated to work in a dynamic start-up environment.
• B.S. degree in Electrical or Computer engineering (or similar field).