Senior Staff Hardware Verification Engineer

Senior Staff Hardware Verification Engineer

Your Role as a Senior Staff Hardware Verification Engineer

As a Senior Staff Hardware Verification Engineer, you will be responsible for verifying a highly configurable and complex IP and/or system, independently, using established verification methodologies.

You will work in demanding technical environments and actively contribute to the continuous improvement of verification flows and methodologies.

Key Responsibilities

• Analyze architectural specifications
• Propose, estimate, and implement a validation strategy for new features in a complete system using UVM methodology
• Extend test suites and define new configurations to validate new functionality
• Update the testbench generation engine to support new features or the latest versions of VIPs, simulators, and compilation tools
• Monitor regression runs, debug tests, and automate reporting of coverage metrics (code and functional coverage)
• Provide support and resolve internal and customer tickets (reported by Application Engineers)
• Improve the verification environment, including flows, processes, and performance

Required Qualifications

• 8–12+ years of experience in digital circuit design and verification
• Strong expertise in creating and debugging RTL testbenches using UVM methodology
• Experience integrating third-party Verification IP (VIP) for unit-level and system-level verification
• Experience with Arm AMBA protocols
• Strong hardware and software programming skills:
  • SystemVerilog
  • Python
  • Java
  • Scala
  • C++
  • JavaScript

• Experience improving verification flows and methodologies
• Master’s degree (Bac+5) or PhD in electronics, computer engineering, or a related field
• Fluent French and English

Senior Staff Hardware Verification Engineer

Your Role as a Senior Staff Hardware Verification Engineer

As a Senior Staff Hardware Verification Engineer, you will be responsible for verifying a highly configurable and complex IP and/or system, independently, using established verification methodologies.

You will work in demanding technical environments and actively contribute to the continuous improvement of verification flows and methodologies.

Key Responsibilities

• Analyze architectural specifications
• Propose, estimate, and implement a validation strategy for new features in a complete system using UVM methodology
• Extend test suites and define new configurations to validate new functionality
• Update the testbench generation engine to support new features or the latest versions of VIPs, simulators, and compilation tools
• Monitor regression runs, debug tests, and automate reporting of coverage metrics (code and functional coverage)
• Provide support and resolve internal and customer tickets (reported by Application Engineers)
• Improve the verification environment, including flows, processes, and performance

Required Qualifications

• 8–12+ years of experience in digital circuit design and verification
• Strong expertise in creating and debugging RTL testbenches using UVM methodology
• Experience integrating third-party Verification IP (VIP) for unit-level and system-level verification
• Experience with Arm AMBA protocols
• Strong hardware and software programming skills:
  • SystemVerilog
  • Python
  • Java
  • Scala
  • C++
  • JavaScript

• Experience improving verification flows and methodologies
• Master’s degree (Bac+5) or PhD in electronics, computer engineering, or a related field
• Fluent French and English