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range of industries within the field of technology
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CPU Research Engineer
CPU Research Engineer (Contractor)
Key Responsibilities:
• Research and develop novel out-of-order execution techniques to improve IPC and energy efficiency of mobile CPUs.
• Analyse and optimise front-end pipeline stages, including branch prediction, fetch, and decode.
• Investigate bottlenecks in the out-of-order backend, including issue queues, register renaming, reorder buffer, and execution units.
• Develop and maintain cycle-accurate micro-architectural simulation models, such as gem5, to evaluate out-of-order design trade-offs.
• Propose micro-architectural enhancements targeting performance-per-watt optimisation for mobile workloads.
• Conduct workload characterisation and micro-architectural profiling using hardware performance counters and simulation.
• Evaluate and integrate state-of-the-art academic research into practical CPU design proposals.
Required:
• Master’s or PhD degree in Computer Science, Computer Engineering, Electrical Engineering, Physics, or a related technical discipline.
• Strong knowledge of advanced computer architectures, superscalar processor design, and compiler design principles.
• Deep understanding of speculative execution, branch prediction, and out-of-order execution.
• Strong programming skills in C, C++, Python, assembly languages such as Arm64 or RISC-V assembly, and scripting languages.
• Experience with cycle-accurate micro-architecture simulation and performance modelling.
• Understanding of instruction scheduling, register allocation, and code generation.
• Highly motivated and independent, with a strong desire for continuous knowledge acquisition.
Desired:
• Strong knowledge of advanced branch predictors and prefetching mechanisms.
• Experience with gem5, Sniper, ChampSim, or other cycle-accurate detailed micro-architecture simulators.
• Experience with LLVM backend development or custom ISA extension implementation.
• Strong knowledge of profile-guided optimisation and feedback-directed optimisation.
• Experience with compiler development, including LLVM, GCC, or compiler optimisation techniques.
• Experience with OS kernel development and understanding of scheduler and memory manager internals.
• Knowledge of binary translation, dynamic binary instrumentation, or JIT compilation techniques.
• Understanding of hardware-enforced security mechanisms such as CFI, PAC, BTI, or MTE.
• Experience with co-simulation frameworks integrating ISA simulators with compiler toolchains.
• Familiarity with emerging technologies such as processing-in-memory, near-data processing, and chiplet architectures.
• Familiarity with domain-specific architectures and accelerator-compiler co-design methodologies.
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