Sr Digital Design Engineer

Recruitment Consultant

Steve Drury

Contact Details

sd@eu-recruit.com +44 (0)330 028 2904

Posted

24 days ago

A fantastic opportunity for an experienced Digital Design Engineer to join a growing MEMS and Analog Semiconductor company, who offer the industry’s most advanced and most reliable timing solutions.

Job Summary

Our client take pride in pushing the innovation boundaries in MEMS and CMOS, using state-of-the-art analog and digital circuits to achieve very aggressive design specs for their timing solutions. Their precision timing products keep pushing the boundaries of the industry across all dimensions, continuously gaining market share.

The digital portion of their chips has been growing in the past few years and is expected to grow more rapidly in the upcoming years as their functionality and features scale up.

To address their unique technical challenges, we are looking for a strong Senior Logic Design Engineer with a solid background in key digital design and implementation areas.

Responsibilities:

Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD)
Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL
Developing standalone test benches to verify the RTL behavior
Writing and verifying SystemVerilog Assertions (SVA) for a design
Writing timing constraints and clock definition for synthesis and place and route tools
Running industry-standard synthesis tools (e.g., Genus or Design Compiler) and being able to fix timing problems if they arise
Understanding various design tradeoffs including timing/area/power and knowing how to improve them
Reading and understanding the Static Timing Analysis (STA) reports from an industry-standard STA tool (e.g., Prime Time)
Cross-functional interactions and communication with various teams within the organisation including analog, verification, backend, system, and test engineering teams
Post-Si bring-up, validation, and debugging

Qualifications & Requirements (Education must be included):

Master’s degree in electrical engineering
5+ years of relevant work experience in the industry
Excellent verbal and written communication skills in English
Proficient in Verilog and SystemVerilog
Expertise in digital logic design fundamentals such as clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etc
Experience in designing mixed-signal digital logic
Basic understanding of Discrete time Signal Processing theory, FIR, and IIR filter design
Solid experience in digital design flow including RTL design, synthesis, timing constraints, and STA
Skilled in scripting languages Perl/Tcl/Python

Industry

Semiconductor

Contract Type

Permanent

Location

Netherlands

City

Delft

Work Model

On-Site

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